DESIGN
W OE VM EBTNA&TI MNT : E TFREPI ECGSHA
Focus of application
Objective
Comment
High speed flash in-system programming
Programming of serial flash (SPI, I2C), FPGA boot-flash, parallel flash (NOR, NAND) Test of the connections between FPGA and RAM (sRAM, dRAM...) Checking of clock signals (single-ended, differential) Test of the connections between FPGA and external MAC/PHY Test of gigabit connections, incl. eye diagram visualisation
Up to 100 times faster than e.g. boundary scan
RAM test
Higher test speed than boundary scan, but same pin- level diagnosis Instrument can also be used for toggle detection
Frequency measurement
LAN test
Protocol-based function test
Bit Error Rate Test (BERT)
Support for parallel transmission channels such as e.g. PCIe x16
Table 1. Examples of ChipVORX applications
(BERT) for GBit links, which can only be performed with a nominal operating speed, or under stress conditions. A purely numeric assessment of transmission quality is inadequate here, and eye diagrams are also required. In order to support such applications, the FPGA suppliers have permanently integrated sophisticated scanning mechanisms (so-called samplers) in the silicon, directly behind the GBit receiver. In this case, the ChipVORX IPs also control these instruments, harmonised with the necessary interface parametrisation and the BERT pattern generators and analysers included in the IP (Figure 5). Since all the TX/Rx settings can be interactively adjusted, without new design synthesis, this also provides the design engineer with an effective means for link validation.
There are different modes for flexible flow control: • Interactive debugging during project creation • Interactive measured value visualisation with confirmation in run-time mode • Standard run-time mode with numeric target/actual comparison of measured values • Control of the overall process by parent entities (system integration) Visualisation of measured values is in the form of panels (Figure 3). The use of FPGA-embedded instruments with the concepts discussed above has
Figure 2. Typical architecture of a BERT-IP ChipVORX
46 ELECTRONICSPECIFIER.COM
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